This invention relates generally to memory control circuits and, more particularly, to an on chip WRITE STROBE signal generator utilizing a unique level detector in combination with standard logic elements.
It is well known that for clock synchronized, pipe-line operated memories, a properly timed WRITE STROBE signal must be generated so as to avoid writing information into erroneous locations of memory. In the past, however, such signals have been generated off-chip (i.e. external to the integrated circuit chip on which the memory is impemented) in accordance with the memory's write enable timing specification. To make clock synchronized memories easier to use and to free the user from the awkward task of providing the appropriate WRITE STROBE signal, it would be desirable to provide circuitry on the memory chip itself which will produce the required signal solely from the system clock regardless of the frequency and duty cycle of the clock.